Can anyone explain the significance of this? I’m pretty technology-literate, but I am not seeing a big advantage of this over any other Linux machine? Genuinely curious.
RISC-V is a set of instructions implementable to processors that do not need licensing fees and controlling restrictions imposed. Due to its reduced instruction set; it uses less power in general but is harder to write compilers that work on it.
Having it more popularised opens up the doors for more enthausists to enter developing with it.
Harder to write compilers for RISC? I would argue that CISC is much harder to design a compiler for.
That being said there’s a lack of standardized vector/streaming instructions in out-of-the-box RISC-V that may hurt performance, but compiler design wise it’s much easier to write a functional compiler than for the nightmare that is x86.
The Vector extension has been ratified since 2021 it’s a standard part of the spec just don’t expect a random microcontroller to support it.
The SpacemiT K1 is 64GCVB and RVA22, doesn’t say which specific RVA22 there’s some without Vector support but it says in “GCVB” so w/e, also, “VLEN 256/128-bit x2 execution width”, if I’m parsing that correctly means you either get 256-bit vector registers or set the whole thing to 128 and then get (roughly) twice the ops/s.
And yes it’s much easier to emit vector code than to deal with the nightmare that’s SIMD. It’s as if Intel would’ve been sensible ages ago and not introduced SIMD but expanded on repnz stosb to make it useful for things other than memcpy. And no Intel has no excuse: Crays existed when they decided on SIMD.
How good are the RISC-V vector instructions implementations IRL? I’ve never heard of them. My experience with ARM is that even on certain data center chips the performance gains are abyssal (when using highly optimized libraries such as dpdk)
It is a Linux machine. Runs a Debian derivative, and it’s not like Windows or anything else that isn’t Linux/BSD can run on a RISC-V laptop.
This isn’t the first RISC-V laptop, but the significance of a RISC-V laptop existing is primarily for developers who work on software targeting RISC-V systems. The ability to run RV64 programs without emulation and to natively compile RV64 software without cross-compilers is valuable to some people. Also, China in particular sees value in having computing products that aren’t affected by sanctions; the processor in this is designed and manufactured by a Chinese company without licensing any intellectual property from US or UK.
Explaining what RISC-V is
RISC-V is a relatively newer CPU instruction set architecture that competes with x86 (Intel, AMD) and ARM (Qualcomm, Ampere, MediaTek, etc.). Its current designs don’t really match those two in general-purpose performance yet but has the distinction of being a free, open, and extendable standard. Whereas x86 has only two CPU vendors and ARM has many vendors who all need to pay per-core license fees to ARM Holdings and have limits imposed on what they can do to it, RISC-V processors can be made by any hardware vendor with the means to make a processor and can be custom-designed to better fit specialized use-cases. Its use in general-purpose CPUs is catching on fastest in China but it sees use across the world in academia and in special-purpose processors by companies like Western Digital.
One of the implications is the development and popularization of the RISC-V architecture, which is open and can open the market for more competition and less monopolies, among other things.
RISC-V is an open source chip design. As of today, it’s still worse than x86 (a CISC—“complex instruction set” design) and ARM (a proprietary RISC—“reduced instruction set” design) but if history is any indication, open source will end up overtaking them in the same way that, for instance, 98% of supercomputers today run highly customized versions of Linux.
There’s also some political connotations surrounding it because some countries don’t want high-end chip designs to be available to their perceived competitors (whether for protectionism reasons or military reasons) but it doesn’t matter.
RISC and CISC are two language which your CPU speaks, and which have different strengths and weaknesses. Reduced Instruction Set Computer vs. Complex Instruction Set Computer. It’s something like Chinese vs. English. Either have a word for everything but that means there is a lot of words to learn, or have a smaller amount of words but that means you need more words to describe what you mean.
Highly technical; both been around for a while, and iirc usually CPUs use CISC, but RISC always retained it’s strengths, so scientists are always looking into the difference in application for both.
Ngl I have no clue why this technology is so newsworthy rn but I know Western countries made a fuss about China activitely pushing the lesser used RISC architecture.
Ngl I have no clue why this technology is so newsworthy rn
It’s because of openness/royalties.
RISC-V is an open standard instruction set architecture based on RISC principles. RISC itself is just a design type. ARM is based on RISC too, but it’s proprietary.
Can anyone explain the significance of this? I’m pretty technology-literate, but I am not seeing a big advantage of this over any other Linux machine? Genuinely curious.
RISC-V is a set of instructions implementable to processors that do not need licensing fees and controlling restrictions imposed. Due to its reduced instruction set; it uses less power in general but is harder to write compilers that work on it.
Having it more popularised opens up the doors for more enthausists to enter developing with it.
Harder to write compilers for RISC? I would argue that CISC is much harder to design a compiler for.
That being said there’s a lack of standardized vector/streaming instructions in out-of-the-box RISC-V that may hurt performance, but compiler design wise it’s much easier to write a functional compiler than for the nightmare that is x86.
The Vector extension has been ratified since 2021 it’s a standard part of the spec just don’t expect a random microcontroller to support it.
The SpacemiT K1 is 64GCVB and RVA22, doesn’t say which specific RVA22 there’s some without Vector support but it says in “GCVB” so w/e, also, “VLEN 256/128-bit x2 execution width”, if I’m parsing that correctly means you either get 256-bit vector registers or set the whole thing to 128 and then get (roughly) twice the ops/s.
And yes it’s much easier to emit vector code than to deal with the nightmare that’s SIMD. It’s as if Intel would’ve been sensible ages ago and not introduced SIMD but expanded on
repnz stosbto make it useful for things other than memcpy. And no Intel has no excuse: Crays existed when they decided on SIMD.How good are the RISC-V vector instructions implementations IRL? I’ve never heard of them. My experience with ARM is that even on certain data center chips the performance gains are abyssal (when using highly optimized libraries such as dpdk)
It is a Linux machine. Runs a Debian derivative, and it’s not like Windows or anything else that isn’t Linux/BSD can run on a RISC-V laptop.
This isn’t the first RISC-V laptop, but the significance of a RISC-V laptop existing is primarily for developers who work on software targeting RISC-V systems. The ability to run RV64 programs without emulation and to natively compile RV64 software without cross-compilers is valuable to some people. Also, China in particular sees value in having computing products that aren’t affected by sanctions; the processor in this is designed and manufactured by a Chinese company without licensing any intellectual property from US or UK.
Explaining what RISC-V is
RISC-V is a relatively newer CPU instruction set architecture that competes with x86 (Intel, AMD) and ARM (Qualcomm, Ampere, MediaTek, etc.). Its current designs don’t really match those two in general-purpose performance yet but has the distinction of being a free, open, and extendable standard. Whereas x86 has only two CPU vendors and ARM has many vendors who all need to pay per-core license fees to ARM Holdings and have limits imposed on what they can do to it, RISC-V processors can be made by any hardware vendor with the means to make a processor and can be custom-designed to better fit specialized use-cases. Its use in general-purpose CPUs is catching on fastest in China but it sees use across the world in academia and in special-purpose processors by companies like Western Digital.
One of the implications is the development and popularization of the RISC-V architecture, which is open and can open the market for more competition and less monopolies, among other things.
RISC-V is a CPU architecture, like x86 or ARM. You can run Linux on it.
RISC-V is an open source chip design. As of today, it’s still worse than x86 (a CISC—“complex instruction set” design) and ARM (a proprietary RISC—“reduced instruction set” design) but if history is any indication, open source will end up overtaking them in the same way that, for instance, 98% of supercomputers today run highly customized versions of Linux.
There’s also some political connotations surrounding it because some countries don’t want high-end chip designs to be available to their perceived competitors (whether for protectionism reasons or military reasons) but it doesn’t matter.
RISC and CISC are two language which your CPU speaks, and which have different strengths and weaknesses. Reduced Instruction Set Computer vs. Complex Instruction Set Computer. It’s something like Chinese vs. English. Either have a word for everything but that means there is a lot of words to learn, or have a smaller amount of words but that means you need more words to describe what you mean.
Highly technical; both been around for a while, and iirc usually CPUs use CISC, but RISC always retained it’s strengths, so scientists are always looking into the difference in application for both.
Ngl I have no clue why this technology is so newsworthy rn but I know Western countries made a fuss about China activitely pushing the lesser used RISC architecture.
It’s because of openness/royalties.
RISC-V is an open standard instruction set architecture based on RISC principles. RISC itself is just a design type. ARM is based on RISC too, but it’s proprietary.
This IS a Linux machine. Do you know what a CPU architecture is?